Date: Wed, 20 Nov 1996 19:17:28 GMT
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<html><head> <title> Design Automation Research Group</title> </head>
<H2> Design Automation Research Group 
<!WA0><img align=Middle src="http://web.cps.msu.edu/img/icons/at_work_icon.gif"> </H2> 
<HR size=5> <!WA1><IMG alt ="" SRC="http://web.cps.msu.edu/img/line.gif"> 
<P> 

Design Automation Research Group is an
inter-departmental and inter-disciplinary group composed faculty from
<!WA2><A Href="http://web.cps.msu.edu"> Computer Science Department</a> and
<!WA3><A Href="http://web.egr.msu.edu/EE/ee.html">Electrical Engineering Department</a>.

The research focus is to promote productivity of engineering system
design using rapidly improving information technology. It includes how
to model the design, manage the design/ manufacturing process, validate
the correctness of design, and support the life cycle of the product.

Research projects have been supported by Government such as
NSF, Air Force and Industries such as Ford.


<HR size=5>

<h3> Faculty  </h3>
<UL>
<!WA4><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.blue.gif">
     <!WA5><A HREF="http://web.cps.msu.edu/~chung">Moon Jung Chung</a><br>
<!WA6><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.blue.gif">
     <!WA7><A HREF="http://web.cps.msu.edu/~wojcik">Anthony Wojcik</a><br>
<!WA8><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.blue.gif">
     <!WA9><A HREF="http://www.egr.msu.edu/~rover">Diane Rover </a><br>
<!WA10><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.blue.gif">
     <!WA11><A HREF = "http://www.egr.msu.edu/~mas">Michele Shanblatt </a><br>
<!WA12><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.blue.gif">
     Chin Long Wey
</UL>   
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<h3>
Research Projects
</h3>
<UL>
<h4> <!WA13><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.gold.gif">
     <!WA14><a href="#Process"> Design Process </a> </h4>
<h4> <!WA15><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.gold.gif">
     <!WA16><a href="#Reengineering">Reengineering of Digital Circuits </a></h4>
<h4> <!WA17><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.gold.gif">
     <!WA18><a href="#Parallel Simulation"> Parallel Simulation </a> </h4>
<h4> <!WA19><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.gold.gif">
     <!WA20><a href="#Verification">
     Verification of Properties of Digital Systems </a></h4>
<h4> <!WA21><IMG ALT="o" SRC="http://web.cps.msu.edu/img/ball.gold.gif">
     <!WA22><a href="#Low Power">
     Improved Placement Methodolgy for Low Power VLSI Circuits </a></h4>
</UL>
<HR size=5>

<UL>
<H3><A NAME="Process">DESIGN PROCESS MANAGEMENT</A></H3>
</UL>
<STRONG>
Principal Investigators: Moon Jung Chung and Anthony Wojcik
</STRONG><br> 
As the complexity of products increases,
companies need to develop solid and effective process management for
various aspects of production, allowing them to promote productivity
and to fully utilize the rapid progress in information technology.
Effective design process management is crucial to the survival of
industries in global competition, especially for the Michigan
automotive industry.  Our approach is based on formal modeling of
design process using process grammar.

This research work has been supported by the Air Force Wright
Patterson Laboratory, and System Engineering Research Institute.


<HR size=5>
<!WA23><IMG alt ="" SRC="http://web.cps.msu.edu/img/line.gif">
<UL>
<H3><A NAME="Parallel Simulation">PARALLEL SIMULATION</A></H3>
</H3>
</UL>
<STRONG>
Principal Investigator: Moon Jung Chung
</STRONG><br> 
Simulation is a bottleneck in a design process. 
The focus of the research is on Parallel VHDL Performance
Simulation. With the support from DoD HPC Modernization Program, 
we are developing a parallel simulation engine targeted for the SP2
machine which can achieve a speed-up up to 100 times compare to
sequential simulation. 
<HR size=5>
<!WA24><IMG alt ="" SRC="http://web.cps.msu.edu/img/line.gif">
<UL>
<H3><A NAME="Reengineering">REENGINEERING OF DIGITAL CIRCUITS </A></H3>
</H3>
</UL>
<STRONG>
Principal Investigators: Anthony Wojcik, Moon Jung Chung, Bill Punch and Jon Sticklen
</STRONG><br>

Of considerable interest in the design automation community is the
problem of reengineering, or redesign, of electronic circuits.  The
basic problem is to take a given design and to respecify or
remanufacture an electronic part, board, or system.  The key problem
is that original design information may be missing or incomplete.
Hence, redesign starts with only partial knowledge of the target
system and must infer original specifications.

Our approach to this problem incorporates the use of formal
methods.  Formal methods refers to the collection of approaches 
based on mathematical logic and formal proof techniques used
for the design and analysis of hardware and software systems.
Our work includes the use of a variety of formal methods
including automated reasoning, genetic algorithms, and knowledge-
based systems.


<HR size=5>
<!WA25><IMG alt ="" SRC="http://web.cps.msu.edu/img/line.gif">
<UL>
<H3><A NAME="VERIFICATION">VERIFICATION OF PROPERTIES OF DIGITAL SYSTEMS
</A></H3>
</H3>
</UL>
<STRONG>
Principal Investigator: Anthony Wojcik
</STRONG><br>

As systems become ever more complex, it becomes increasingly
important to be able to verify properties about systems.
Clearly, one property is that the system functionally implements
the intended specification.  However, there are
other properties of interest, including fault-tolerance and
security.  A critical problem is the modeling of properties
of systems and then the verification of the properties.  It
is clear that simulation alone cannot be used to verify properties.
For that reason, the use of formal methods continues to be of
great importance.

Formal methods refers to the collection of approaches based on 
mathematical logic and formal proof techniques used for the design
and analysis of hardware and software systems.  Our work is concerned
both with the use of appropriate representations for modeling
systems and properties of systems, and the application of 
techniques incorporating automated reasoning systems, Prolog and 
other approaches in order to prove properties of systems.

<HR size=5>
<!WA26><IMG alt ="" SRC="http://web.cps.msu.edu/img/line.gif">
<UL>
<H3><A NAME="Low Power">
Improved Placement Methodolgy for Low Power VLSI Circuits </a></h3>
</UL>
<STRONG>
Principal Investigator: Michael Shanblatt <br> 
Graduate Student:
Manuel Jimenez 
</STRONG><br> 
Reducing the amount of power dissipated by integrated circuits has
become an issue of major concern in the design of digital VLSI
systems. Among the factors pushing for power efficient circuits are
the tight energy budgets of portable computing and commu-nication
devices, the reliability concerns of the circuits themselves, and the
packaging and cooling costs associated with power hungry devices.
This project involves the development of a new placement approach in
very large scale integration (VLSI) designs aimed at producing layouts
of circuits with reduced power dissipation. More specifically, a
placement methodology for digital VLSI circuits is under development,
whose objectives include minimizing the power dissipation of the
resulting circuit while maintaining the estimated wire length and
layout within pre-established bounds.

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